Senior Staff Verification Engineer


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San Jose, CA 



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Employment Type:

Full time



Job Description:

Xilinx is the world's leading provider of All Programmable FPGAs, SoCs and 3D ICs. These industry-leading devices are coupled with a next-generation design environment and IP to serve a broad range of customer needs, from programmable logic to programmable systems integration. Our All Programmable devices underpin today's most advanced electronics. Among the broad range of end markets we serve are: 
  • Aerospace/Defense
  • Automotive
  • Broadcast
  • Consumer
  • High Performance Computing
  • Industrial / Scientific / Medical (ISM)
  • Wired
  • Wireless

Xilinx FDST Verification group is looking for a seasoned verification engineer to verify high speed SerDes design. The individual will help design, develop and use simulation and verification environments, at block and full chip FPGA level, to prove the functional correctness of SerDes designs.
The ideal candidate is one who has a proven track record on driving strategies and successful verification execution on high performance IP and/or VLSI designs.
Require BS w/ 9+ yrs or MS w/ 7+ yrs or PhD w/ 5+ yrs in Electrical Engineering, Computer Engineering or Computer Science.
Candidate is expected to be a strong team player with good communication and leadership skills and one who is able to positively and strategically influence the SerDes design and verification teams with an eye towards improving overall product quality.
Require experience with development of UVM, OVM, VMM and/or Verilog, System Verilog test benches and usage of simulation tools/debug environments.
Require strong understanding of state of the art of verification techniques, including assertion and metric-driven verification.
Require familiarity with verification management tools as well as understanding of database management particularly as it pertains to regression management.
Strong understanding of different phases of ASIC and/or full custom chip development is required.
Experience as a verification architect, establishing the verification methodology, tools and infrastructure for high performance IP and/or VLSI designs is a plus.
Experience with mixed-signal verification tools and methodology as well as analog behavioral modeling is a big plus.
Experience with DSP and communication system designs is a plus.
Experience with formal property checking tools such as Cadence (IEV), Jasper and Synopsys (Magellan) is a plus.
Experience with gate level simulation, power verification, reset verification, contention checking, abstraction techniques is a plus.
Company Info
2100 Logic Dr.
San Jose, CA, United States

Phone: (408) 879-6085
Web Site: www.xilinx.com

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